meeting date: 4 oct 2005
attending: Arpad Muranyi, Barry Katz, Ian Dodd, Bob Ross,
           Ken Willis, Mike LaBonte
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Review of ARs:

AR: Ken get List of Cadence/Telian customers willing to try it
- TBD, need to contact specifically IC companies

AR: All review library for completeness
- to be discussed in this meeting

AR: Mike will annotate library modules
- about 25% done, ongoing

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ASICS
- Can we get ASIC designers to use this?
  - Most ASIC designers do not design custom buffers.

File naming for website
- Should file names be dated?
  - Website should only have the latest

Node name order and spelling
- Is IBIS buffer module naming OK?
  - IBIS params are case-sensitive
  - Leave out '-' in 3-state and '/' in I/O
  - Names will be all uppercase
- Do we need ECL?
  - Existing implementations may fail
  - Hold off for now
- HSPICE terminal order is OK

Syntax alternatives for native Verilog-A buffer implementation
- 'define' syntax in external files can be tricky
- How to pass IBIS filename and modelname for simulators not using
  this code?
  - Converter could recreate B element from the data
- HSPICE 2005.09 has problems with some of this syntax

People need to try out Arpad's files
  -Is LibNet.cml missing?
  - hsp-model-cache

PWL Source
- Needs filename or array for data input
  - Can use same include mechanism for this

Can we eliminate current-controlled elements?
- Could use voltage-controlled with sense resistor
  - But then the sense resistor would have non-zero R

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Next meeting: Tuesday 11 oct 2005.